Telescopic units: a new paradigm for performance optimization of VLSI designs

2 ADD-Based Timing Analysis The problem of calculatin& the timing r8poose of a combin... tionallogic block can be formulated as follows: GiYen a combinational block, find the set of input vectors for which the length of the critical path, under a .pecified mode of operation and a gate delay model, is maximum; the length of the critical path gi~ the overall block delay. Given a gate g of the network and an input vector % EX, where X i. the set of all the C4fe input vectors of the block, the arrival time at ita output line, AT(g,z), i. evaluated in terms of the arrival timea of its inputs, and the delays of ita fanin connectiona, d(cj,z). Let Cj be the connection to pin j of gate g. If all fanina of g have noD-controlling valua: AT(g,~) = max{AT(Ci'~) + d(Ci'~)} J